The Energy-Efficient Circuits and Intelligent Systems Group (EECIS) at the Department of Information Technology and Electrical Engineering (D-ITET), ETH Zurich, is offering a doctoral or postdoctoral position. This role is part of an international industry-academia research project focused on developing next-generation single-chip RGB-D image sensors for robotics.
Scholarship Details
| Organization | ETH Zurich |
| Department | Department of Information Technology and Electrical Engineering (D-ITET) |
| Designation | Doctoral or Postdoctoral Position |
| Research Area | Low-jitter frequency synthesis and clock generation |
| Location | Zurich, Switzerland |
| Employment Type | 100%, Fixed-term |
| Application Deadline | November 30 |
Research Area
The research focuses on the core analog building blocks of a monolithic RGB-D sensor System-on-Chip (SoC). Specifically, the position targets the development of on-chip clock generators, including phase-locked loops (PLL) operating with ultra-low jitter and very low power consumption, to support direct time-of-flight (dToF) depth sensing.
Scholarship Description
The successful candidate will contribute to the development of a next-generation single-chip RGB-D image sensor that combines color imaging with direct time-of-flight depth sensing on a single-photon avalanche diode (SPAD) array. Key responsibilities include:
- Developing architecture and system-level specifications for low-jitter, low-power PLLs.
- Investigating new techniques for energy-efficient frequency synthesis and clock distribution.
- Designing, laying out, and taping out circuits in advanced CMOS technology.
- Characterizing chips in the measurement lab and refining designs based on results.
- Publishing research at leading international conferences and journals.
- Contributing to the teaching activities of the EECIS group.
Eligibility/Qualification
Applicants must meet the following criteria:
- A Master’s or Ph.D. degree in electrical engineering or a closely related field with excellent academic grades.
- A solid background in analog and mixed-signal integrated circuit design.
- Experience with PLLs, oscillators, clock generation, or data converters is highly advantageous.
- Hands-on experience with Cadence Virtuoso or similar IC design tools.
- Previous tape-out or lab measurement experience is preferred.
- Strong analytical skills and the ability to work independently within an international team.
- Excellent proficiency in written and spoken English.
How to Apply
Applications must be submitted exclusively through the ETH Zurich online application portal. Emailed or postal applications will not be considered. Please prepare the following documents for your submission:
- A motivation letter (maximum 1 page) describing your interest and relevant experience.
- A current Curriculum Vitae (CV), including a list of publications if applicable.
- Copies of Bachelor’s and Master’s degree certificates and academic transcripts.
- Contact information for two professional references.
Apply Link: Apply Online Now
Last Date for Apply
The application deadline is November 30. The anticipated start date is November 1, 2027, or upon agreement.
